The present invention relates generally to logic circuits and more particularly to logic circuits with dimensions scaled for performance enhancement.
Tremendous effort has been spent to increase the speed of electronic circuits. One approach is to combine the strengths of Metal-Oxide-Semiconductor (MOS) and bipolar technologies. Typically, MOS devices control the logic of a circuit and bipolar devices increase the output current drive capability, which in turn increases the speed of the circuit. Commonly used circuits with such configurations are BiNMOS and BiCMOS circuits.
The configuration of a BiNMOS or a BiCMOS circuit involves a pull-up section and a pull-down section. The pull-up section "pulls the circuit up" so that the output voltage of the circuit is at a high logic level; the pull-down section "pulls the circuit down" so that the output voltage of the circuit is at a low logic level. Both the BiNMOS and the BiCMOS circuits have MOS devices in the pull-up and the pull-down sections. The main difference between the two types of circuits is that the BiCMOS circuit has bipolar devices in both the pull-up and the pull-down sections, whereas the BiNMOS circuit has bipolar devices only in the pull-up section.
Raje et al. in "A New Method for Design of BiCMOS Gates and Comparison with CMOS" have disclosed a method to increase the speed of a BiCMOS logic circuit. The method relates a characteristic dimension of the bipolar devices in the circuit to a characteristic dimension of the MOS devices in the circuit by a pre-determined ratio. With the ratio, one only has to design either the MOS or the bipolar devices, and the other devices are automatically designed. However, there is still a need to further increase the speed of circuits with such configurations and to further reduce the complexity of designing such circuits.